Verilog Coding for Logic Synthesis

Copyright © 2003 John Wiley & Sons, Inc.

Verilog Coding for Logic Synthesis

Author(s): Weng Fook Lee

Published Online: 28 JAN 2005

Print ISBN: 9780471429760

Online ISBN: 9780471457565

DOI: 10.1002/0471457566

About this Book

Product Information

About The Product

Provides a practical approach to Verilog design and problem solving.
* Bulk of the book deals with practical design problems that design engineers solve on a daily basis.
* Includes over 90 design examples.
* There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.
* Book is suitable for use as a textbook in EE departments that have VLSI courses

Table of contents

    1. You have free access to this content
      Frontmatter (pages i–xxvi)

    2. Chapter 1

      Introduction (pages 1–2)

    3. Chapter 2

      ASIC Design Flow (pages 3–15)

    4. Chapter 3

      Verilog Coding (pages 16–40)

    5. Chapter 4

      Coding Style: Best-Known Method for Synthesis (pages 41–150)

    6. Chapter 5

      Design Example of Programmable Timer (pages 151–180)

    7. Chapter 6

      Design Example of Programmable Logic Block for Peripheral Interface (pages 181–292)

    8. You have free access to this content
      Appendix (pages 293–304)

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      Glossary (pages 305–306)

    10. You have free access to this content
      Bibliography (page 307)

    11. You have free access to this content
      Index (pages 308–309)

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