Advanced Interconnects for ULSI Technology

Advanced Interconnects for ULSI Technology

Editor(s): Mikhail R. Baklanov, Paul S. Ho, Ehrenfried Zschech

Published Online: 17 FEB 2012 04:38AM EST

Print ISBN: 9780470662540

Online ISBN: 9781119963677

DOI: 10.1002/9781119963677

About this Book

Finding new materials for copper/low-k interconnects is critical to the continuing development of computer chips. While copper/low-k interconnects have served well, allowing for the creation of Ultra Large Scale Integration (ULSI) devices which combine over a billion transistors onto a single chip, the increased resistance and RC-delay at the smaller scale has become a significant factor affecting chip performance.

Advanced Interconnects for ULSI Technology is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects, and discusses:

  • Interconnect functions, characterisations, electrical properties and wiring requirements
  • Low-k materials: fundamentals, advances and mechanical  properties
  • Conductive layers and barriers
  • Integration and reliability including mechanical reliability, electromigration and electrical breakdown
  • New approaches including 3D, optical, wireless interchip, and carbon-based interconnects

Intended for postgraduate students and researchers, in academia and industry, this book provides a critical overview of the enabling technology at the heart of the future development of computer chips.

Table of contents

    1. You have free access to this content
    1. You have free access to this content
  1. Section I: Low-k Materials

    1. Chapter 2

      Ultra-Low-k by CVD: Deposition and Curing (pages 35–77)

      Vincent Jousseaume, Aziz Zenasni, Olivier Gourhant, Laurent Favennec and Mikhail R. Baklanov

    2. Chapter 3

      Plasma Processing of Low-k Dielectrics (pages 79–128)

      Hualiang Shi, Denis Shamiryan, Jean-François de Marneffe, Huai Huang, Paul S. Ho and Mikhail R. Baklanov

    3. Chapter 4

      Wet Clean Applications in Porous Low-k Patterning Processes (pages 129–171)

      Quoc Toan Le, Guy Vereecke, Herbert Struyf, Els Kesters and Mikhail R. Baklanov

  2. Section II: Conductive Layers and Barriers

  3. Section III: Integration and Reliability

  4. Section IV: New Approaches

    1. Chapter 12

      3D Interconnect Technology (pages 435–490)

      John U. Knickerbocker, Lay Wai Kong, Sven Niese, Alain Diebold and Ehrenfried Zschech

    2. Chapter 13

      Carbon Nanotubes for Interconnects (pages 491–502)

      Mizuhisa Nihei, Motonobu Sato, Akio Kawabata, Shintaro Sato and Yuji Awano

    1. You have free access to this content

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