Chapter 10. DSP System Implementation

  1. Heinrich Meyr,
  2. Marc Moeneclaey and
  3. Stefan A. Fechtel

Published Online: 9 OCT 2001

DOI: 10.1002/0471200573.ch10

Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing

Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing

How to Cite

Meyr, H., Moeneclaey, M. and Fechtel, S. A. (2001) DSP System Implementation, in Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing, John Wiley & Sons, Inc., New York, USA. doi: 10.1002/0471200573.ch10

Publication History

  1. Published Online: 9 OCT 2001

Book Series:

  1. Wiley Series in Telecommunications and Signal Processing

Book Series Editors:

  1. John G. Proakis

Series Editor Information

  1. Northeastern University

ISBN Information

Print ISBN: 9780471502753

Online ISBN: 9780471200574

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Keywords:

  • digital signal processing (DSP);
  • system implementation;
  • hardware;
  • software;
  • design;
  • quantization;
  • number representation;
  • ASIC design case study;
  • bit error;
  • performance;
  • DVP chip;
  • implementation;
  • CAD tools;
  • coding;
  • decoding;
  • Reed-Solomon detectors;
  • Viterbi detectors

Summary

This chapter is concerned with the implementation of digital signal processing systems. It serves the purpose to make the algorithm designer aware of the strong interaction between algorithm and architecture design.

Digital signal processing systems are an assembly of heterogeneous hardware components. The functionality is implemented in both hardware and software subsystems. A brief overview of DSP hardware technology is given. Design time and cost become increasingly more important than chip cost. Hardware-software co-design and quantization issues are discussed. An ASIC (application-specific integrated circuit) design of a fully digital receiver is discussed. We describe the design flow of the project, the receiver structure, and the decision making for its building blocks. Two sections are bibliographical notes on Viterbi and Reed-Solomon decoders.