Chapter 5. Packet Fair Queuing Implementations
Published Online: 12 FEB 2002
DOI: 10.1002/0471224391.ch5
Copyright © 2002 by John Wiley & Sons, Inc.
Book Title
Quality of Service Control in High-Speed Networks
Additional Information
How to Cite
Chao, H. J. and Guo, X. (2002) Packet Fair Queuing Implementations, in Quality of Service Control in High-Speed Networks, John Wiley & Sons, Inc., New York, USA. doi: 10.1002/0471224391.ch5
Publication History
- Published Online: 12 FEB 2002
- Published Print: 1 NOV 2001
ISBN Information
Print ISBN: 9780471003977
Online ISBN: 9780471224396
- Summary
- Chapter
Keywords:
- packet scheduling;
- packet fair queuing (PFQ);
- delay bound;
- arrival process;
- departure process;
- timestamp;
- searching and sorting;
- Sequencer;
- priority content addressable memory (PCAM);
- RAM-based searching engine (RSE);
- 2-D RSE;
- shaper-scheduler;
- finite bit overflow
Summary
Chapter 5 describes several architectures to implement packet fair queuing (PFQ) algorithms for a large number of connections and high-speed links. Very large scale integration (VLSI) chips are introduced. The Sequencer chip and the priority content addressable memory (PCAM) chip can be used to sort timestamp values and to find the smallest timestamp value, respectively. A RAM-based searching engine (RSE) that is both scalable and cost-effective is described, and a general shaper-scheduler using RSE and two-dimensional RSE (2-D RSE) is introduced. Details of implementation are discussed. The timestamp aging problem due to finite bit overflow is also addressed.