Chapter 5. Packet Fair Queuing Implementations

  1. H. Jonathan Chao Ph.D.1 and
  2. Xiaolei Guo Ph.D.2

Published Online: 12 FEB 2002

DOI: 10.1002/0471224391.ch5

Quality of Service Control in High-Speed Networks

Quality of Service Control in High-Speed Networks

How to Cite

Chao, H. J. and Guo, X. (2002) Packet Fair Queuing Implementations, in Quality of Service Control in High-Speed Networks, John Wiley & Sons, Inc., New York, USA. doi: 10.1002/0471224391.ch5

Author Information

  1. 1

    Polytechnic University, Brooklyn, New York, USA

  2. 2

    INTEC Systems, Manalapan, New Jersey, USA

Publication History

  1. Published Online: 12 FEB 2002
  2. Published Print: 1 NOV 2001

ISBN Information

Print ISBN: 9780471003977

Online ISBN: 9780471224396

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Keywords:

  • packet scheduling;
  • packet fair queuing (PFQ);
  • delay bound;
  • arrival process;
  • departure process;
  • timestamp;
  • searching and sorting;
  • Sequencer;
  • priority content addressable memory (PCAM);
  • RAM-based searching engine (RSE);
  • 2-D RSE;
  • shaper-scheduler;
  • finite bit overflow

Summary

Chapter 5 describes several architectures to implement packet fair queuing (PFQ) algorithms for a large number of connections and high-speed links. Very large scale integration (VLSI) chips are introduced. The Sequencer chip and the priority content addressable memory (PCAM) chip can be used to sort timestamp values and to find the smallest timestamp value, respectively. A RAM-based searching engine (RSE) that is both scalable and cost-effective is described, and a general shaper-scheduler using RSE and two-dimensional RSE (2-D RSE) is introduced. Details of implementation are discussed. The timestamp aging problem due to finite bit overflow is also addressed.