Chapter 3. Input-Buffered Switches

  1. H. Jonathan Chao Ph.D.1,
  2. Cheuk H. Lam Ph.D.2 and
  3. Eiji Oki Ph.D.3

Published Online: 18 FEB 2002

DOI: 10.1002/0471224405.ch3

Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers

Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers

How to Cite

Chao, H. J., Lam, C. H. and Oki, E. (2001) Input-Buffered Switches, in Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers, John Wiley & Sons, Inc., New York, USA. doi: 10.1002/0471224405.ch3

Author Information

  1. 1

    Polytechnic University, Brooklyn, New York, USA

  2. 2

    Lucent Technologies, Inc., Landover, Maryland, USA

  3. 3

    NTT Network Service Systems Laboratories, Tokyo, Japan

Publication History

  1. Published Online: 18 FEB 2002
  2. Published Print: 1 SEP 2001

ISBN Information

Print ISBN: 9780471004547

Online ISBN: 9780471224402

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Keywords:

  • input-buffered switch;
  • head-of-line blocking;
  • Bernoulli process;
  • on-off model;
  • input smoothing;
  • speedup;
  • look-ahead selection;
  • virtual-output-queueing;
  • arbitration;
  • matching;
  • iterative round-robin;
  • dual round-robin;
  • bi-directional arbiter;
  • token-tunneling;
  • output-queueing emulation

Summary

Chapter 3 covers the fundamentals of input-buffered switches, including the head-of-line blocking phenomenon, traffic models and related throughput results, methods for performance improving, and scheduling algorithms. We show the problems of input-buffered switches, and present the techniques and algorithms that have been proposed to tackle the problems.