8. Design-For-Testability

  1. Alexander Miczo

Published Online: 29 AUG 2003

DOI: 10.1002/0471457787.ch8

Digital Logic Testing and Simulation, Second Edition

Digital Logic Testing and Simulation, Second Edition

How to Cite

Miczo, A. (2003) Design-For-Testability, in Digital Logic Testing and Simulation, Second Edition, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471457787.ch8

Publication History

  1. Published Online: 29 AUG 2003
  2. Published Print: 15 AUG 2003

ISBN Information

Print ISBN: 9780471439950

Online ISBN: 9780471457787

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Keywords:

  • design-for-testability (DFT);
  • rules;
  • controllability/observability analysis;
  • scan path;
  • partial scan path;
  • PCBs;
  • scan solutions

Summary

We begin by considering some circuit configurations that cause problems in digital circuits. This is followed by an examination of techniques used to improve controllability and observability. Later, we look at formal methods for DFT (design-for-test-ability) methodology.