6. Synchronization and Memory Consistency

  1. Tarek El-Ghazawi1,
  2. William Carlson2,
  3. Thomas Sterling3 and
  4. Katherine Yelick4

Published Online: 27 JAN 2005

DOI: 10.1002/0471478369.ch6

UPC: Distributed Shared Memory Programming

UPC: Distributed Shared Memory Programming

How to Cite

El-Ghazawi, T., Carlson, W., Sterling, T. and Yelick, K. (2005) Synchronization and Memory Consistency, in UPC: Distributed Shared Memory Programming, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471478369.ch6

Author Information

  1. 1

    The George Washington University, USA

  2. 2

    IDA Center for Computing Sciences, USA

  3. 3

    California Institute of Technology, USA

  4. 4

    University of California at Berkeley, USA

Publication History

  1. Published Online: 27 JAN 2005
  2. Published Print: 13 MAY 2005

Book Series:

  1. Wiley Series on Parallel and Distributed Computing

Book Series Editors:

  1. Albert Y. Zomaya

ISBN Information

Print ISBN: 9780471220480

Online ISBN: 9780471478362



  • barrier synchronization;
  • locks;
  • memory consistency


UPC is a parallel processing language, which requires coordination among the executing threads. Therefore, UPC provides for synchronization and memory consistency control. Examples of these mechanisms are barriers, locks, and fences. UPC barriers can ensure that all threads reach a given point before any of them can proceed any further. Locks are needed to coordinate accesses to critical sections of the code. Finally, memory consistency control gives the ability to control the access ordering to memory by the different threads such that performance can be maximized with no risk of data inconsistency. Memory consistency mechanisms in UPC also give the programmer the ability to decide when changes to a shared object become visible to other threads.