Chapter 1. Nano-CMOS Scaling Problems and Implications

  1. Ban P. Wong1,
  2. Anurag Mittal2,
  3. Yu Cao3 and
  4. Greg Starr4

Published Online: 27 JAN 2005

DOI: 10.1002/0471653829.ch1

Nano-CMOS Circuit and Physical Design

Nano-CMOS Circuit and Physical Design

How to Cite

Wong, B. P., Mittal, A., Cao, Y. and Starr, G. (2004) Nano-CMOS Scaling Problems and Implications, in Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471653829.ch1

Author Information

  1. 1

    NVIDIA, USA

  2. 2

    Virage Logic, Inc., USA

  3. 3

    University of California-Berkeley, USA

  4. 4

    Xilinx, USA

Publication History

  1. Published Online: 27 JAN 2005
  2. Published Print: 12 NOV 2004

ISBN Information

Print ISBN: 9780471466109

Online ISBN: 9780471653820

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Keywords:

  • Moore's law;
  • physical scaling near limit;
  • sub-wavelength lithography;
  • sub-wavelength gap;
  • resolution extension technology;
  • BEOL;
  • low-k;
  • interconnect FOM;
  • CMP dishing and erosion;
  • FEOL;
  • source drain extension resistance;
  • transistor FOM;
  • STI stress induced mobility degradation;
  • strain silicon;
  • δ W;
  • DIBL;
  • statistical dopant fluctuation;
  • raised source drain technology;
  • CET;
  • EOT;
  • process control and reliability;
  • LER;
  • NBTI;
  • poly depletion;
  • optical proximity correction;
  • design methodology;
  • mask data explosion;
  • GIDL;
  • sub-threshold leakage;
  • modeling challenges;
  • scalability;
  • manufacturability;
  • mask cost;
  • variation tolerance;
  • proximity effects;
  • RSC;
  • DITS;
  • direct tunneling;
  • well proximity effect

Summary

Chapter 1 provides a brief overview of the challenges facing the circuit and physical designers in the nano-CMOS technology nodes and the need for a paradigm shift in the design methodology that can effectively deal with the pitfalls as a result of the new and newly exacerbated physical effects due to process scaling. This chapter also expounds on the need for circuit and physical design engineers to be aware of and understand the effects brought about by aggressive dimensional scaling, in order to be able to take advantage of such a technology and to ensure functional and robust designs. As mask costs increase it is even more urgent that designers understand these effects so as to avoid the pitfalls in order to achieve a functional design on first silicon.