Chapter 10. Design for Manufacturability

  1. Ban P. Wong1,
  2. Anurag Mittal2,
  3. Yu Cao3 and
  4. Greg Starr4

Published Online: 27 JAN 2005

DOI: 10.1002/0471653829.ch10

Nano-CMOS Circuit and Physical Design

Nano-CMOS Circuit and Physical Design

How to Cite

Wong, B. P., Mittal, A., Cao, Y. and Starr, G. (2005) Design for Manufacturability, in Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471653829.ch10

Author Information

  1. 1

    NVIDIA, USA

  2. 2

    Virage Logic, Inc., USA

  3. 3

    University of California-Berkeley, USA

  4. 4

    Xilinx, USA

Publication History

  1. Published Online: 27 JAN 2005
  2. Published Print: 12 NOV 2004

ISBN Information

Print ISBN: 9780471466109

Online ISBN: 9780471653820

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Keywords:

  • DFM;
  • OPC;
  • resolution extension technologies;
  • NBTI;
  • parameter variability;
  • process variation;
  • alignment offset;
  • end-cap coverage;
  • diffusion flaring;
  • phase shift masking;
  • low-κ dielectric;
  • signal integrity;
  • wire spreading;
  • poly gate flaring;
  • channel length;
  • scatter bars;
  • PLL;
  • loop filter;
  • STI;
  • erosion;
  • Nwell proximity effects;
  • polygon density;
  • manufacturable;
  • variation robust

Summary

Chapter 10 provides guidelines for achieving a manufacturable and high performance design. Numerous examples including post OPC simulations are shown of potential issues with the physical layout of circuits along with methods for improvements. This chapter starts with a discussion for the need of DFM techniques embedded in designs for the nano-CMOS technologies. Then some case studies of sub-optimal layouts and how they can be improved are presented along with the issues created by the sub-optimal layouts. The chapter also covers analog and global route DFM techniques and some rules of thumb.