Chapter 11. Design for Variability

  1. Ban P. Wong1,
  2. Anurag Mittal2,
  3. Yu Cao3 and
  4. Greg Starr4

Published Online: 27 JAN 2005

DOI: 10.1002/0471653829.ch11

Nano-CMOS Circuit and Physical Design

Nano-CMOS Circuit and Physical Design

How to Cite

Wong, B. P., Mittal, A., Cao, Y. and Starr, G. (2004) Design for Variability, in Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471653829.ch11

Author Information

  1. 1


  2. 2

    Virage Logic, Inc., USA

  3. 3

    University of California-Berkeley, USA

  4. 4

    Xilinx, USA

Publication History

  1. Published Online: 27 JAN 2005
  2. Published Print: 12 NOV 2004

ISBN Information

Print ISBN: 9780471466109

Online ISBN: 9780471653820



  • manufacturability;
  • yield;
  • parametric variations;
  • clock distribution;
  • skew;
  • optical proximity correction;
  • layout;
  • self timing;
  • statistical modeling


Chapter 11 investigates the looming challenges of silicon process variations to robust circuit design. As the increasing variations significantly degrade design quality, it is critical to consider manufacturability and yield factors at the design stage. Design strategies to mitigate their impacts are examined, ranging from specific designs of clock distribution and memory units, to more general approaches of robust analog and digital designs for nano-CMOS technology. Besides design techniques for manufacturability, statistical analysis of circuit performance is also presented, in order to effectively handle process variations and improve system yield.