Chapter 2. CMOS Device and Process Technology

  1. Ban P. Wong1,
  2. Anurag Mittal2,
  3. Yu Cao3 and
  4. Greg Starr4

Published Online: 27 JAN 2005

DOI: 10.1002/0471653829.ch2

Nano-CMOS Circuit and Physical Design

Nano-CMOS Circuit and Physical Design

How to Cite

Wong, B. P., Mittal, A., Cao, Y. and Starr, G. (2004) CMOS Device and Process Technology, in Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471653829.ch2

Author Information

  1. 1


  2. 2

    Virage Logic, Inc., USA

  3. 3

    University of California-Berkeley, USA

  4. 4

    Xilinx, USA

Publication History

  1. Published Online: 27 JAN 2005
  2. Published Print: 12 NOV 2004

ISBN Information

Print ISBN: 9780471466109

Online ISBN: 9780471653820



  • interconnect;
  • gate dielectric;
  • strained silicon;
  • rapid thermal processing;
  • short-channel effect;
  • metal gate;
  • gate leakage;
  • parasitics capacitance;
  • reliability;
  • damascene process;
  • CMP;
  • low-κ dielectric


Chapter 2 outlines the latest advances in silicon process technology, covering both frontend devices and backend interconnects. Despite of tremendous design benefits from these technology innovations, severe challenges have been posed to both process developers and circuit designers in the nanometer regime, such as gate dielectric integration, strained silicon engineering, leakage control, source/drain parasitics reduction, device reliability, metal resistivity control, interconnect planarization, and low-κ dielectric integration. Possible solutions and limitations are investigated in this chapter, in order to continue the success of technology scaling.