Chapter 4. Mixed-Signal Circuit Design

  1. Ban P. Wong1,
  2. Anurag Mittal2,
  3. Yu Cao3 and
  4. Greg Starr4

Published Online: 27 JAN 2005

DOI: 10.1002/0471653829.ch4

Nano-CMOS Circuit and Physical Design

Nano-CMOS Circuit and Physical Design

How to Cite

Wong, B. P., Mittal, A., Cao, Y. and Starr, G. (2004) Mixed-Signal Circuit Design, in Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471653829.ch4

Author Information

  1. 1

    NVIDIA, USA

  2. 2

    Virage Logic, Inc., USA

  3. 3

    University of California-Berkeley, USA

  4. 4

    Xilinx, USA

Publication History

  1. Published Online: 27 JAN 2005
  2. Published Print: 12 NOV 2004

ISBN Information

Print ISBN: 9780471466109

Online ISBN: 9780471653820

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Keywords:

  • shallow trench isolation stress;
  • analog;
  • mixed signal;
  • gate leakage;
  • guard ring;
  • power bus;
  • inductor;
  • capacitor;
  • level shifter;
  • low voltage;
  • bandgap;
  • ESD;
  • electrostatic discharge;
  • decoupling

Summary

Chapter 4 provides a brief overview of the issues facing mixed signal circuits and provides guidance for avoiding some of the pitfalls associated with designing circuits on these advanced processes. While detailed circuit descriptions are not provided, some general guidelines and options are presented through the use of examples to help designers to understand the trade-offs that need to be considered to ensure a functional design is implemented. Process issues that affect the performance of analog circuits are discussed at length. Integration issues within a larger digital chip, such as noise coupling, power busing, supply decoupling, and thermal issues, are also discussed.