Chapter 6. Input/Output Design

  1. Ban P. Wong1,
  2. Anurag Mittal2,
  3. Yu Cao3 and
  4. Greg Starr4

Published Online: 27 JAN 2005

DOI: 10.1002/0471653829.ch6

Nano-CMOS Circuit and Physical Design

Nano-CMOS Circuit and Physical Design

How to Cite

Wong, B. P., Mittal, A., Cao, Y. and Starr, G. (2004) Input/Output Design, in Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471653829.ch6

Author Information

  1. 1

    NVIDIA, USA

  2. 2

    Virage Logic, Inc., USA

  3. 3

    University of California-Berkeley, USA

  4. 4

    Xilinx, USA

Publication History

  1. Published Online: 27 JAN 2005
  2. Published Print: 12 NOV 2004

ISBN Information

Print ISBN: 9780471466109

Online ISBN: 9780471653820

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Keywords:

  • low voltage differential signal;
  • single ended;
  • current mode logic;
  • active inductor;
  • PAM;
  • pulse amplitude modulation;
  • ESD;
  • electrostatic discharge;
  • simultaneous switching noise;
  • decoupling;
  • termination;
  • pre-emphasis;
  • equalization

Summary

Chapter 6 outlines the current trends in I/O buffer design. An overview of the various IO specifications is provided along with the current trends for implementing the designs. Power bussing issues and simultaneous switching noise issues are discussed at length to illustrate the importance of developing the IO power bus scheme up front. On-die decoupling is also discussed at length, as this is becoming a key feature required to meet the high-speed interface specifications.