Chapter 7. DRAM

  1. Ban P. Wong1,
  2. Anurag Mittal2,
  3. Yu Cao3 and
  4. Greg Starr4

Published Online: 27 JAN 2005

DOI: 10.1002/0471653829.ch7

Nano-CMOS Circuit and Physical Design

Nano-CMOS Circuit and Physical Design

How to Cite

Wong, B. P., Mittal, A., Cao, Y. and Starr, G. (2004) DRAM, in Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471653829.ch7

Author Information

  1. 1

    NVIDIA, USA

  2. 2

    Virage Logic, Inc., USA

  3. 3

    University of California-Berkeley, USA

  4. 4

    Xilinx, USA

Publication History

  1. Published Online: 27 JAN 2005
  2. Published Print: 12 NOV 2004

ISBN Information

Print ISBN: 9780471466109

Online ISBN: 9780471653820

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Keywords:

  • DRAM;
  • three dimensional 1T1C cell;
  • word-line;
  • bit-lines;
  • storage capacitor;
  • access transistor;
  • sense amplifier;
  • folded bit-line architecture;
  • multiplexer;
  • equalizer;
  • precharge;
  • cross-coupled;
  • planarize;
  • stack cell;
  • trench cell;
  • capacitance enhancement techniques;
  • sub-100 nm technologies;
  • off-state leakage;
  • mobility;
  • GIDL;
  • data retention;
  • sub-threshold slope;
  • dual-gate oxide thickness devices;
  • planar;
  • two-dimensional capacitor;
  • three-dimensional vertical capacitor

Summary

Chapter 7 takes the reader through the basics of DRAM design and then goes into the techniques to successfully scale the storage capacitor, access transistor and sense amplifier into the nano-CMOS processes. It begins with an introduction into the DRAM basics for non-DRAM designers so that they too can appreciate the concepts presented later in the chapter. The scaling of the major components of the DRAM, the storage capacitor, the array transistors and the sense amplifier is discussed in detail, including the issues and solutions.