Chapter 8. Signal Integrity Problems in On-Chip Interconnects

  1. Ban P. Wong1,
  2. Anurag Mittal2,
  3. Yu Cao3 and
  4. Greg Starr4

Published Online: 27 JAN 2005

DOI: 10.1002/0471653829.ch8

Nano-CMOS Circuit and Physical Design

Nano-CMOS Circuit and Physical Design

How to Cite

Wong, B. P., Mittal, A., Cao, Y. and Starr, G. (2004) Signal Integrity Problems in On-Chip Interconnects, in Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471653829.ch8

Author Information

  1. 1

    NVIDIA, USA

  2. 2

    Virage Logic, Inc., USA

  3. 3

    University of California-Berkeley, USA

  4. 4

    Xilinx, USA

Publication History

  1. Published Online: 27 JAN 2005
  2. Published Print: 12 NOV 2004

ISBN Information

Print ISBN: 9780471466109

Online ISBN: 9780471653820

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Keywords:

  • signal integrity;
  • timing analysis;
  • crosstalk noise;
  • slew rate;
  • overshoot;
  • inductance;
  • capacitance;
  • driver;
  • repeater;
  • shielding;
  • differential signal

Summary

Chapter 8 addresses the signal integrity issues in high-speed interconnect design. Physical principles of parasitics extraction and electrical analysis are discussed, providing a variety of analytical approaches that efficiently optimize the design of signal paths. Besides an overview of signal timing and crosstalk issues, particular discussions focus on interconnect inductance effects and noise-aware timing analysis. Practical solutions are also introduced from both physical and circuit design perspectives, including noise-constrained driver and line tuning, repeater and booster design, and differential signal techniques.