Chapter 8. Signal Integrity Problems in On-Chip Interconnects
Published Online: 27 JAN 2005
Copyright © 2005 John Wiley & Sons, Inc.
Nano-CMOS Circuit and Physical Design
How to Cite
Wong, B. P., Mittal, A., Cao, Y. and Starr, G. (2004) Signal Integrity Problems in On-Chip Interconnects, in Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471653829.ch8
- Published Online: 27 JAN 2005
- Published Print: 12 NOV 2004
Print ISBN: 9780471466109
Online ISBN: 9780471653820
- signal integrity;
- timing analysis;
- crosstalk noise;
- slew rate;
- differential signal
Chapter 8 addresses the signal integrity issues in high-speed interconnect design. Physical principles of parasitics extraction and electrical analysis are discussed, providing a variety of analytical approaches that efficiently optimize the design of signal paths. Besides an overview of signal timing and crosstalk issues, particular discussions focus on interconnect inductance effects and noise-aware timing analysis. Practical solutions are also introduced from both physical and circuit design perspectives, including noise-constrained driver and line tuning, repeater and booster design, and differential signal techniques.