Chapter 9. Ultralow Power Circuit Design

  1. Ban P. Wong1,
  2. Anurag Mittal2,
  3. Yu Cao3 and
  4. Greg Starr4

Published Online: 27 JAN 2005

DOI: 10.1002/0471653829.ch9

Nano-CMOS Circuit and Physical Design

Nano-CMOS Circuit and Physical Design

How to Cite

Wong, B. P., Mittal, A., Cao, Y. and Starr, G. (2004) Ultralow Power Circuit Design, in Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/0471653829.ch9

Author Information

  1. 1

    NVIDIA, USA

  2. 2

    Virage Logic, Inc., USA

  3. 3

    University of California-Berkeley, USA

  4. 4

    Xilinx, USA

Publication History

  1. Published Online: 27 JAN 2005
  2. Published Print: 12 NOV 2004

ISBN Information

Print ISBN: 9780471466109

Online ISBN: 9780471653820

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Keywords:

  • ultra low-power;
  • leakage;
  • SRAM;
  • DRAM;
  • interconnect power;
  • design-time;
  • run-time;
  • supply voltage;
  • threshold voltage;
  • charging capacitance;
  • stack effect;
  • FinFET

Summary

Chapter 9 presents an overview of system- and circuit-level design techniques to effectively reduce chip power consumption, especially the standby power of memory units. At design-time, ultra low-power memory design (i.e., SRAM and DRAM) can be achieved by reducing charging capacitance, scaling supply voltage, and optimizing operation schemes. At run-time, adaptive control of supply and threshold voltages is exploited to aggressively suppress leakage power. Furthermore, this chapter also discusses emerging technology innovations that help to minimize power consumption in the nanometer regime, such as FinFET and assembly technologies.