Chapter 6. Latchup of Parasitic Thyristor in IGBT

  1. Vinod Kumar Khanna

Published Online: 28 JAN 2005

DOI: 10.1002/047172291X.ch6

Insulated Gate Bipolar Transistor IGBT Theory and Design

Insulated Gate Bipolar Transistor IGBT Theory and Design

How to Cite

Khanna, V. K. (2003) Latchup of Parasitic Thyristor in IGBT, in Insulated Gate Bipolar Transistor IGBT Theory and Design, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/047172291X.ch6

Author Information

  1. Pilani, India

Publication History

  1. Published Online: 28 JAN 2005
  2. Published Print: 5 AUG 2003

ISBN Information

Print ISBN: 9780471238454

Online ISBN: 9780471722915

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Keywords:

  • latching;
  • PNP and NPN transistors;
  • parasitic thyristors

Summary

  • Introduction

  • Static Latching

  • Dynamic Latching

  • Latching Prevention Measures

  • Latching Current Density of Trench–Gate IGBT

  • Summarizing Remarks

  • Review Exercises

  • References

  • Appendix 6.1 Equation (6.15)

  • Appendix 6.2 Equation (6.20)