4. All-Digital Phase-Locked Loop

  1. Robert Bogdan Staszewski1 and
  2. Poras T. Balsara2

Published Online: 19 DEC 2005

DOI: 10.1002/9780470041956.ch4

All-Digital Frequency Synthesizer in Deep-Submicron CMOS

All-Digital Frequency Synthesizer in Deep-Submicron CMOS

How to Cite

Staszewski, R. B. and Balsara, P. T. (2006) All-Digital Phase-Locked Loop, in All-Digital Frequency Synthesizer in Deep-Submicron CMOS, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/9780470041956.ch4

Author Information

  1. 1

    Texas Instruments, USA

  2. 2

    University of Texas at Dallas, USA

Publication History

  1. Published Online: 19 DEC 2005
  2. Published Print: 31 AUG 2006

ISBN Information

Print ISBN: 9780471772552

Online ISBN: 9780470041956

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Keywords:

  • frequency reference retiming by a DCO clock;
  • loop gain factor;
  • all-digital phase-locked-loop (ADPLL)–based frequency synthesizer

Summary

This chapter contains sections titled:

  • Phase-Domain Operation

  • Reference Clock Retiming

  • Phase Detection

  • Modulo Arithmetic of the Reference and Variable Phases

  • Time-to-Digital Converter

  • Fractional Error Estimator

  • Frequency Reference Retiming by a DCO Clock

  • Loop Gain Factor

  • Phase-Domain ADPLL Architecture

  • PLL Frequency Response

  • Noise and Error Sources

  • Type II ADPLL

  • Higher-Order ADPLL

  • Nonlinear Differential Term of an ADPLL

  • DCO Gain Estimation Using a PLL

  • Gear Shifting of PLL Gain

  • Edge Skipping Dithering Scheme (Optional)

  • Summary