Standard Article

Logic Synthesis

  1. Angel Barriga,
  2. Carlos J. Jimenez,
  3. Manuel Valencia

Published Online: 14 DEC 2007

DOI: 10.1002/9780470050118.ecse227

Wiley Encyclopedia of Computer Science and Engineering

Wiley Encyclopedia of Computer Science and Engineering

How to Cite

Barriga, A., Jimenez, C. J. and Valencia, M. 2007. Logic Synthesis. Wiley Encyclopedia of Computer Science and Engineering. .

Author Information

  1. University of Seville-Institute of Microelectronics of Seville, CNM-CSIC, Seville, Spain

Publication History

  1. Published Online: 14 DEC 2007

Abstract

This article addresses logic synthesis, which involves the generation of a circuit at the logic level based on an RT level design specification. The article deals with aspects associated with logic design such as data types, system components, and modes of operation. The hardware description languages will be presented as tools to specify digital systems. Two standard languages (VHDL and Verilog) will be examined in detail, and the use of VHDL for automatic synthesis will be explained to illustrate specific aspects of logic synthesis descriptions. The article ends with an illustrative example of the principal concepts discussed.

Keywords:

  • logic synthesis;
  • register transfer;
  • hardware description language;
  • automatic synthesis;
  • VHDL;
  • verilog;
  • data path;
  • control unit