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Reduced Instruction Set Computing

  1. Vojin G. Oklobdzija

Published Online: 16 MAR 2009

DOI: 10.1002/9780470050118.ecse357

Wiley Encyclopedia of Computer Science and Engineering

Wiley Encyclopedia of Computer Science and Engineering

How to Cite

Oklobdzija, V. G. 2009. Reduced Instruction Set Computing. Wiley Encyclopedia of Computer Science and Engineering. 2381–2390.

Author Information

  1. Integration Corporation, Berkeley, California

Publication History

  1. Published Online: 16 MAR 2009

Abstract

Reduced instruction set computing (RISC) architecture started as a fresh look at existing ideas. The main featue of RISC is the architectural support for the exploitation of parallelism on the instruction level. All distinguished features of RISC should be considered in light of their support for the RISC pipeline.

Keywords:

  • IBM 801;
  • RISC;
  • computer architecture;
  • load/store architecture;
  • instruction sets;
  • pipelining;
  • superscalar machines;
  • superpipeline machines;
  • optimizing compiler;
  • branch and execute;
  • delayed branch;
  • cache;
  • Harvard architecture;
  • delayed load;
  • superscalar;
  • superpipelined