Chapter 3. Interaction of Layout with Transistor Performance and Stress Engineering Techniques
Published Online: 7 FEB 2008
Copyright © 2009 John Wiley & Sons, Inc.
Nano-CMOS Design for Manufacturabililty: Robust Circuit and Physical Design for Sub-65 nm Technology Nodes
How to Cite
Wong, B., Zach, F., Moroz, V., Mittal, A., Starr, G. and Kahng, A. (2008) Interaction of Layout with Transistor Performance and Stress Engineering Techniques, in Nano-CMOS Design for Manufacturabililty: Robust Circuit and Physical Design for Sub-65 nm Technology Nodes, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/9780470382820.ch3
- Published Online: 7 FEB 2008
- Published Print: 6 OCT 2008
Print ISBN: 9780470112809
Online ISBN: 9780470382820
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