Chapter 3. Interaction of Layout with Transistor Performance and Stress Engineering Techniques

  1. Ban Wong,
  2. Franz Zach,
  3. Victor Moroz,
  4. Anurag Mittal,
  5. Greg Starr and
  6. Andrew Kahng

Published Online: 7 FEB 2008

DOI: 10.1002/9780470382820.ch3

Nano-CMOS Design for Manufacturabililty: Robust Circuit and Physical Design for Sub-65 nm Technology Nodes

Nano-CMOS Design for Manufacturabililty: Robust Circuit and Physical Design for Sub-65 nm Technology Nodes

How to Cite

Wong, B., Zach, F., Moroz, V., Mittal, A., Starr, G. and Kahng, A. (2008) Interaction of Layout with Transistor Performance and Stress Engineering Techniques, in Nano-CMOS Design for Manufacturabililty: Robust Circuit and Physical Design for Sub-65 nm Technology Nodes, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/9780470382820.ch3

Publication History

  1. Published Online: 7 FEB 2008
  2. Published Print: 6 OCT 2008

ISBN Information

Print ISBN: 9780470112809

Online ISBN: 9780470382820

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Keywords:

  • layout interaction with transistor performance;
  • stress memorization technique (SMT);
  • intentional stress introduction into transistors

Summary

This chapter contains sections titled:

  • Introduction

  • Impact of Stress on Transistor Performance

  • Stress Propagation

  • Stress Sources

  • Introducing Stress into Transistors

  • References