Chapter 3. Interaction of Layout with Transistor Performance and Stress Engineering Techniques
Published Online: 7 FEB 2008
DOI: 10.1002/9780470382820.ch3
Copyright © 2009 John Wiley & Sons, Inc.
Book Title
Nano-CMOS Design for Manufacturabililty: Robust Circuit and Physical Design for Sub-65 nm Technology Nodes
Additional Information
How to Cite
Wong, B., Zach, F., Moroz, V., Mittal, A., Starr, G. and Kahng, A. (2008) Interaction of Layout with Transistor Performance and Stress Engineering Techniques, in Nano-CMOS Design for Manufacturabililty: Robust Circuit and Physical Design for Sub-65 nm Technology Nodes, John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/9780470382820.ch3
Publication History
- Published Online: 7 FEB 2008
- Published Print: 6 OCT 2008
ISBN Information
Print ISBN: 9780470112809
Online ISBN: 9780470382820
- Summary
- Chapter
- References
Keywords:
- layout interaction with transistor performance;
- stress memorization technique (SMT);
- intentional stress introduction into transistors
Summary
This chapter contains sections titled:
Introduction
Impact of Stress on Transistor Performance
Stress Propagation
Stress Sources
Introducing Stress into Transistors
References