10. Fault- and Defect-Tolerant Architectures for Nanocomputing

  1. Dr. Mary Mehrnoosh Eshaghian-Wilner Adjunct Professor
  1. Sumit Ahuja Research Assistant1,
  2. Gaurav Singh1,
  3. Debayan Bhaduri Research Assistant1 and
  4. Sandeep Shukla Associate Professor2

Published Online: 24 NOV 2009

DOI: 10.1002/9780470429983.ch10

Bio-Inspired and Nanoscale Integrated Computing

Bio-Inspired and Nanoscale Integrated Computing

How to Cite

Ahuja, S., Singh, G., Bhaduri, D. and Shukla, S. (2009) Fault- and Defect-Tolerant Architectures for Nanocomputing, in Bio-Inspired and Nanoscale Integrated Computing (ed M. M. Eshaghian-Wilner), John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/9780470429983.ch10

Editor Information

  1. Department of Electrical Engineering, University of California, Los Angeles, California, USA

Author Information

  1. 1

    Fermat Lab, Virginia Polytechnic and State University, Blacksburg, Virginia, USA

  2. 2

    Department of Electrical and Computer Engineering, Virginia Polytechnic and State University, Blacksburg, Virginia, USA

Publication History

  1. Published Online: 24 NOV 2009
  2. Published Print: 29 MAY 2009

ISBN Information

Print ISBN: 9780470116593

Online ISBN: 9780470429983

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Keywords:

  • fault- and defect-tolerant architectures in nanocomputing;
  • fault tolerance through redundancy;
  • reliability evaluation of defect/fault-tolerant nanocomputing

Summary

This chapter contains sections titled:

  • Introduction

  • Fault Tolerance through Redundancy

  • Defect Tolerance through Reconfiguration

  • Reliability Evaluation of Defect/Fault-Tolerant Nanocomputing

  • Conclusions

  • References