13. Testing, Tuning and Debugging

  1. Donald G. Bailey

Published Online: 2 JUN 2011

DOI: 10.1002/9780470828519.ch13

Design for Embedded Image Processing on FPGAs

Design for Embedded Image Processing on FPGAs

How to Cite

Bailey, D. G. (2011) Testing, Tuning and Debugging, in Design for Embedded Image Processing on FPGAs, John Wiley & Sons (Asia) Pte Ltd, Singapore. doi: 10.1002/9780470828519.ch13

Author Information

  1. Massey University, New Zealand

Publication History

  1. Published Online: 2 JUN 2011
  2. Published Print: 1 JUN 2011

ISBN Information

Print ISBN: 9780470828496

Online ISBN: 9780470828519



  • field programmable gate array (FPGA);
  • image processing;
  • parallelism


There are four main causes for an algorithm not behaving in the intended manner that are addressed briefly in this chapter. These are: Design errors, Implementation errors, Tuning errors and Timing errors. The design of an image processing algorithm for a particular task is a heuristic process. The parallel nature of field programmable gate array (FPGA)-based designs can result in additional bugs not commonly encountered in software-based systems. If the software version of the algorithm behaves correctly then there are two primary sources of error within the corresponding hardware implementation. The first relates to customisation of data word widths and the second relates to the use of parallelism with consequent synchronisation and conflict issues. Timing and timing closure are not just considerations at the end of the implementation, but need to be considered at all aspects of a design, from the initial specification all the way through design and implementation.

Controlled Vocabulary Terms

field programmable gate arrays; image processing