2. Field Programmable Gate Arrays

  1. Donald G. Bailey

Published Online: 2 JUN 2011

DOI: 10.1002/9780470828519.ch2

Design for Embedded Image Processing on FPGAs

Design for Embedded Image Processing on FPGAs

How to Cite

Bailey, D. G. (2011) Field Programmable Gate Arrays, in Design for Embedded Image Processing on FPGAs, John Wiley & Sons (Asia) Pte Ltd, Singapore. doi: 10.1002/9780470828519.ch2

Author Information

  1. Massey University, New Zealand

Publication History

  1. Published Online: 2 JUN 2011
  2. Published Print: 1 JUN 2011

ISBN Information

Print ISBN: 9780470828496

Online ISBN: 9780470828519

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Keywords:

  • development boards;
  • field programmable gate arrays (FPGAs);
  • image processing

Summary

In this chapter, the basic architectural features of Field Programmable Gate Arrays (FPGAs) are examined. While a detailed understanding of the internal architecture of an FPGA is not essential to programme them (the vendor-specific place and route tools manage most of these details), a basic knowledge of the internal structure and how a design maps onto that architecture can be used to develop a more efficient implementation. Logical parallelism within an image processing operation is well suited to FPGA implementation, and it is here where many image processing algorithms may be accelerated significantly. Since an FPGA implements the logic required by an application by building separate hardware for each function, FPGAs are inherently parallel. The particular characteristics of devices from several manufacturers are considered in more detail. Many FPGA manufacturers also sell development boards or evaluation boards.

Controlled Vocabulary Terms

field programmable gate arrays; image processing