5. Mapping Techniques

  1. Donald G. Bailey

Published Online: 2 JUN 2011

DOI: 10.1002/9780470828519.ch5

Design for Embedded Image Processing on FPGAs

Design for Embedded Image Processing on FPGAs

How to Cite

Bailey, D. G. (2011) Mapping Techniques, in Design for Embedded Image Processing on FPGAs, John Wiley & Sons (Asia) Pte Ltd, Singapore. doi: 10.1002/9780470828519.ch5

Author Information

  1. Massey University, New Zealand

Publication History

  1. Published Online: 2 JUN 2011
  2. Published Print: 1 JUN 2011

ISBN Information

Print ISBN: 9780470828496

Online ISBN: 9780470828519



  • field programmable gate array (FPGA);
  • low level pipelining;
  • memory bandwidth


This chapter reviews a range of techniques for mapping from a software algorithm to a hardware implementation. These techniques may be considered as a set of design patterns that provides ways of overcoming common problems or constraints encountered in the mapping process. Timing constraints focus on the limited time available for performing the required operations. One technique for improving throughput is to use low level pipelining. Custom caching can significantly reduce the number of times that the data needs to be loaded into the field programmable gate array (FPGA). Memory bandwidth constraints result from the fact that only one memory access may be made per clock cycle. Any concurrent system with shared resources will face contention when a resource is used by multiple processes. If necessary, the FPGA can be dynamically reconfigured to switch from one task to another.