44. Efficient Resampling Implementations

  1. Richard G. Lyons
  1. Douglas W. Barker

Published Online: 11 JUN 2012

DOI: 10.1002/9781118316948.ch44

Streamlining Digital Signal Processing: A Tricks of the Trade Guidebook, Second Edition

Streamlining Digital Signal Processing: A Tricks of the Trade Guidebook, Second Edition

How to Cite

Barker, D. W. (2012) Efficient Resampling Implementations, in Streamlining Digital Signal Processing: A Tricks of the Trade Guidebook, Second Edition (ed R. G. Lyons), John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/9781118316948.ch44

Editor Information

  1. Besser Associates, Mountain View, California, USA

Author Information

  1. ITT Corporation, White Plains, New York, USA

Publication History

  1. Published Online: 11 JUN 2012
  2. Published Print: 22 JUN 2012

ISBN Information

Print ISBN: 9781118278383

Online ISBN: 9781118316948

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Keywords:

  • efficient resampling, minimizing the resamplers' timing jitter errors;
  • interpolation by arbitrary factor, ROM address generation and ROM addresses;
  • interpolation coefficient computation;
  • resampling, hardware multipliers in FPGA's and RAM for coefficient storage

Summary

This chapter contains sections titled:

  • Resampling Using Polyphase Filters

  • Resampling by an Integer Factor

  • Resampling by an Arbitrary Factor

  • Interpolation by an Arbitrary Factor

  • Computation of the Interpolation Coefficients

  • Decimation by an Arbitrary Factor

  • Computation of the Decimation Coefficients

  • Alternate Method for Computing Decimation Coefficients

  • FPGA Implementation Issues

  • Conclusions

  • References

  • Editor Comment