1. Low Power Multicore Processors for Embedded Systems

  1. Krzysztof Iniewski
  1. Fumio Arakawa

Published Online: 6 NOV 2012

DOI: 10.1002/9781118468654.ch1

Embedded Systems: Hardware, Design, and Implementation

Embedded Systems: Hardware, Design, and Implementation

How to Cite

Arakawa, F. (2012) Low Power Multicore Processors for Embedded Systems, in Embedded Systems: Hardware, Design, and Implementation (ed K. Iniewski), John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/9781118468654.ch1

Editor Information

  1. CMOS Emerging Technologies Research, USA

Author Information

  1. Renesas Electronics Corporation, Tokyo, Japan

Publication History

  1. Published Online: 6 NOV 2012
  2. Published Print: 14 DEC 2012

ISBN Information

Print ISBN: 9781118352151

Online ISBN: 9781118468654

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Keywords:

  • low power multicore processors, for embedded systems;
  • multicore chip with highly efficient cores;
  • SH-X FPU, efficient FPU architecture of SH processors;
  • SH-X3, multicore architecture extension;
  • SH-X4, ISA address space/efficient extension

Summary

This chapter contains sections titled:

  • Multicore Chip with Highly Efficient Cores

  • SuperH™ RISC Engine Family (SH) Processor Cores

  • SH-X: A Highly Efficient CPU Core

  • SH-X FPU: A Highly Efficient FPU

  • SH-X2: Frequency and Efficiency Enhanced Core

  • SH-X3: Multicore Architecture Extension

  • SH-X4: ISA and Address Space Extension

  • References