10. Hybrid Partially Adaptive Fault-Tolerant Routing for 3D Networks-on-Chip

  1. Krzysztof Iniewski
  1. Sudeep Pasricha and
  2. Yong Zou

Published Online: 6 NOV 2012

DOI: 10.1002/9781118468654.ch10

Embedded Systems: Hardware, Design, and Implementation

Embedded Systems: Hardware, Design, and Implementation

How to Cite

Pasricha, S. and Zou, Y. (2012) Hybrid Partially Adaptive Fault-Tolerant Routing for 3D Networks-on-Chip, in Embedded Systems: Hardware, Design, and Implementation (ed K. Iniewski), John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/9781118468654.ch10

Editor Information

  1. CMOS Emerging Technologies Research, USA

Author Information

  1. Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, CO, USA

Publication History

  1. Published Online: 6 NOV 2012
  2. Published Print: 14 DEC 2012

ISBN Information

Print ISBN: 9781118352151

Online ISBN: 9781118468654

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Keywords:

  • hybrid partially adaptive fault-tolerant for 3D networks-on-chip;
  • proposed 4NP-First routing scheme, 3D turn models;
  • existing FT routing schemes, experiments, comparison;
  • 3D-ICs, likelihood of failure from permanent/intermittent faults;
  • 4NP-First for 3D NoCs, 4N-First and 4P-First turn models

Summary

This chapter contains sections titled:

  • Introduction

  • Related Work

  • Proposed 4NP-First Routing Scheme

  • Experiments

  • Conclusion

  • References