11. Electrical Breakdown in Advanced Interconnect Dielectrics

  1. Mikhail R. Baklanov3,
  2. Paul S. Ho4 and
  3. Ehrenfried Zschech5
  1. Ennis T. Ogawa1 and
  2. Oliver Aubel2

Published Online: 17 FEB 2012

DOI: 10.1002/9781119963677.ch11

Advanced Interconnects for ULSI Technology

Advanced Interconnects for ULSI Technology

How to Cite

Ogawa, E. T. and Aubel, O. (2012) Electrical Breakdown in Advanced Interconnect Dielectrics, in Advanced Interconnects for ULSI Technology (eds M. R. Baklanov, P. S. Ho and E. Zschech), John Wiley & Sons, Ltd, Chichester, UK. doi: 10.1002/9781119963677.ch11

Editor Information

  1. 3

    IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

  2. 4

    Lab for Interconnect and Packaging, The University of Texas at Austin, UT-PRC 10100 Burnet Road, Bldg 160, Mail Code R8650, Austin, TX 78758, USA

  3. 5

    Fraunhofer Institute for Non-Destructive Testing IZFP, Dresden Branch, Maria-Reiche-Strasse 2, 01109 Dresden, Germany

Author Information

  1. 1

    Broadcom Corporation, Irvine, CA 92617, USA

  2. 2

    GLOBALFOUNDRIES, Dresden Module One LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany

Publication History

  1. Published Online: 17 FEB 2012
  2. Published Print: 24 FEB 2012

ISBN Information

Print ISBN: 9780470662540

Online ISBN: 9781119963677



  • intermetal dielectric (IMD) time-dependent dielectric breakdown (TDDB);
  • interlevel dielectric (ILD) time-dependent dielectric breakdown;
  • constant voltage stress (CVS);
  • bias temperature stress (BTS);
  • low-k (LK);
  • ultra-low-k (ULK);
  • extreme low-k (ELK) reliability;
  • interconnect dielectric breakdown;
  • low-permittivity dielectric breakdown;
  • ramped voltage dielectric breakdown (RVDB)


Dielectric breakdown in low-k dielectrics is considered one of the major reliability concerns in advanced CMOS process development. The concerns have arisen because of a number of factors: (1) a generally relentless development pace is necessary for interconnect dimensional scaling to meet projected performance needs; (2) a dual-damascene metallization scheme is a difficult process and integration challenge when combined with scaling demands; (3) new dielectric materials need to be incorporated into the back-end-of-line (BEOL) stack to address performance requirements; and (4) advances and improvements associated with new insights into the breakdown physics of BEOL dielectrics identified with dual-damascene integration of low-k materials require careful reassessment of overall interconnect reliability. These concerns|–|along with the underlying detailed list of specifications that will need to be addressed for such concerns|–|pose a formidable challenge to those who are presently developing such advanced technologies. This chapter describes both the present understanding about dielectric breakdown in Cu/low-k interconnect systems and dielectric reliability challenges that remain as advanced interconnects approach sub-32 nm dimensions.