12. 3D Interconnect Technology

  1. Mikhail R. Baklanov3,
  2. Paul S. Ho4 and
  3. Ehrenfried Zschech5
  1. John U. Knickerbocker1,
  2. Lay Wai Kong2,
  3. Sven Niese5,
  4. Alain Diebold2 and
  5. Ehrenfried Zschech5

Published Online: 17 FEB 2012

DOI: 10.1002/9781119963677.ch12

Advanced Interconnects for ULSI Technology

Advanced Interconnects for ULSI Technology

How to Cite

Knickerbocker, J. U., Kong, L. W., Niese, S., Diebold, A. and Zschech, E. (2012) 3D Interconnect Technology, in Advanced Interconnects for ULSI Technology (eds M. R. Baklanov, P. S. Ho and E. Zschech), John Wiley & Sons, Ltd, Chichester, UK. doi: 10.1002/9781119963677.ch12

Editor Information

  1. 3

    IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

  2. 4

    Lab for Interconnect and Packaging, The University of Texas at Austin, UT-PRC 10100 Burnet Road, Bldg 160, Mail Code R8650, Austin, TX 78758, USA

  3. 5

    Fraunhofer Institute for Non-Destructive Testing IZFP, Dresden Branch, Maria-Reiche-Strasse 2, 01109 Dresden, Germany

Author Information

  1. 1

    IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY 10598, USA

  2. 2

    College of Nanoscale Science and Engineering at the University at Albany, Albany, New York, USA

  3. 5

    Fraunhofer Institute for Non-Destructive Testing IZFP, Dresden Branch, Maria-Reiche-Strasse 2, 01109 Dresden, Germany

Publication History

  1. Published Online: 17 FEB 2012
  2. Published Print: 24 FEB 2012

ISBN Information

Print ISBN: 9780470662540

Online ISBN: 9781119963677

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Keywords:

  • 3D interconnects;
  • heterogeneous die;
  • 3D technology;
  • through-silicon vias (TSVs);
  • 3D interconnects;
  • scanning acoustic microscopy (SAM);
  • confocal infrared (IR) microscopy;
  • bonded wafer pairs;
  • high-resolution X-ray computed tomography (XCT)

Summary

Three-dimensional interconnected circuits (3DIC) offer great advantages for system applications. Examples of system advantages from silicon integration technologies can include: power reduction, performance improvements, product miniaturization, cost reduction, modular design for heterogeneous die and improved time to market. In order to take advantage of these 3D system benefits, the design and architecture circuits need to be optimized to take advantage of emerging 3D technology. In addition, the materials, processes and assembly of stacked die and integration of 3D modules, including power delivery, test and cooling, need to be able to be manufactured at cost-effective yields and meet system reliability requirements. 3D stacked die can be integrated using traditional packaging laminate or ceramic packaging or can use emerging silicon and glass packages for higher bandwidth leveraging higher wiring density between die and/or stacked die in multichip modules. Therefore, to optimize system applications leveraging 3D interconnections, ongoing technical challenges include: (i) 3D system design and architecture, (ii) wafer fabrication with through-silicon vias (TSVs), (iii) wafer finishing including wafer thinning, thin wafer handling and wafer backside processing, (iv) assembly using die-to-die, die-to-wafer or wafer-to-wafer stacking, (v) wafer test and burn-in, (vi) power delivery, (vii) cooling and (viii) module integration. This chapter will explore the system opportunities and technical challenges related to 3D silicon interconnections in systems. Examples of 3D test vehicles, data and results are reported for the technical challenges used in 3D design, wafer fabrication and module integration.

The rapid development of the 3D IC stacking technology is driving the need for advances in microscopy methods. Overlay measurements after wafer bonding, defect detection and void inspection after copper plating are challenging due to the need to image through silicon and inside copper. Microscopy techniques for which silicon is not opaque, such as scanning acoustic microscopy (SAM) and confocal infrared (IR) microscopy, are capable of inspecting the interface between bonded wafer pairs, while high-resolution X-ray computed tomography (XCT) is used to detect voids in metal TSVs. This chapter covers several analytical techniques for process and quality control. The current status of SAM, IR microscopy and nano-XCT, complemented by techniques for microstructure characterization, is discussed in terms of their application to process metrology and failure analysis for 3D IC integration.