5. Copper Electroplating for On-Chip Metallization

  1. Mikhail R. Baklanov2,
  2. Paul S. Ho3 and
  3. Ehrenfried Zschech4
  1. Valery M. Dubin

Published Online: 17 FEB 2012

DOI: 10.1002/9781119963677.ch5

Advanced Interconnects for ULSI Technology

Advanced Interconnects for ULSI Technology

How to Cite

Dubin, V. M. (2012) Copper Electroplating for On-Chip Metallization, in Advanced Interconnects for ULSI Technology (eds M. R. Baklanov, P. S. Ho and E. Zschech), John Wiley & Sons, Ltd, Chichester, UK. doi: 10.1002/9781119963677.ch5

Editor Information

  1. 2

    IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

  2. 3

    Lab for Interconnect and Packaging, The University of Texas at Austin, UT-PRC 10100 Burnet Road, Bldg 160, Mail Code R8650, Austin, TX 78758, USA

  3. 4

    Fraunhofer Institute for Non-Destructive Testing IZFP, Dresden Branch, Maria-Reiche-Strasse 2, 01109 Dresden, Germany

Author Information

  1. NANO3D SYSTEMS LLC, Portland, Oregon, USA

Publication History

  1. Published Online: 17 FEB 2012
  2. Published Print: 24 FEB 2012

ISBN Information

Print ISBN: 9780470662540

Online ISBN: 9781119963677

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Keywords:

  • copper;
  • electroplating;
  • electroless plating;
  • damascene interconnects

Summary

The chapter covers the copper plating for interconnect applications. The models explaining electroplating superfill phenomena have been reviewed including the roles of accelerator, suppressor and leveler. Alternative copper plating techniques such as electroless plating and direct plating have also been discussed. Electroplating copper properties including resistivity, impurities and electromigration resistance were summarized. Key references give the reader further resources.