7. Process Integration of Interconnects
- Mikhail R. Baklanov2,
- Paul S. Ho3,
- Ehrenfried Zschech4
Published Online: 17 FEB 2012
DOI: 10.1002/9781119963677.ch7
Copyright © 2012 John Wiley & Sons, Ltd
Book Title
Advanced Interconnects for ULSI Technology
Additional Information
How to Cite
Balakrishnan, S., Brain, R. and Zhao, L. (2012) Process Integration of Interconnects, in Advanced Interconnects for ULSI Technology (eds M. R. Baklanov, P. S. Ho and E. Zschech), John Wiley & Sons, Ltd, Chichester, UK. doi: 10.1002/9781119963677.ch7
Editor Information
- 2
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
- 3
Lab for Interconnect and Packaging, The University of Texas at Austin, UT-PRC 10100 Burnet Road, Bldg 160, Mail Code R8650, Austin, TX 78758, USA
- 4
Fraunhofer Institute for Non-Destructive Testing IZFP, Dresden Branch, Maria-Reiche-Strasse 2, 01109 Dresden, Germany
Publication History
- Published Online: 17 FEB 2012
- Published Print: 24 FEB 2012
ISBN Information
Print ISBN: 9780470662540
Online ISBN: 9781119963677
- Summary
- Chapter
- References
Keywords:
- low-k;
- air-gap;
- interconnect;
- integration;
- Cu resistivity;
- narrow lines resistivity;
- barriers;
- electromigration
Summary
This chapter aims to introduce the reader to the challenges of on-die interconnect integration as the semiconductor industry continues to march down the scaling path, with leading companies exercising high-volume production at 45 nm and lower nodes as of 2010. Before we dive into the state-of-the-art technology nodes, a brief review of the progression of complexity and incorporation of novel materials into the on-die interconnect architecture during the last twenty years should prove beneficial.