1. Scaling and Limitation of Si-Based CMOS

  1. Prof. Gang He and
  2. Prof. Zhaoqi Sun
  1. Prof. Gang He2,
  2. Prof. Zhaoqi Sun2,
  3. Mao Liu1 and
  4. Lide Zhang1

Published Online: 23 AUG 2012

DOI: 10.1002/9783527646340.ch1

High-k Gate Dielectrics for CMOS Technology

High-k Gate Dielectrics for CMOS Technology

How to Cite

He, G., Sun, Z., Liu, M. and Zhang, L. (2012) Scaling and Limitation of Si-Based CMOS, in High-k Gate Dielectrics for CMOS Technology (eds G. He and Z. Sun), Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim, Germany. doi: 10.1002/9783527646340.ch1

Editor Information

  1. Anhui University, School of Physics and Materials Science, Anhui Key Laboratory of Information Materials and Devices, Feixi Road 3, Hefei 230039, China

Author Information

  1. 1

    Chinese Academy of Sciences, Institute of Solid State Physics, Anhui Key Laboratory of Nanomaterials and Nanostructure, Key Lab of Materials Physics, Hefei 230031, China

  2. 2

    Anhui University, School of Physics and Materials Science, Anhui Key Laboratory of Information Materials and Devices, Feixi Road 3, Hefei 230039, China

Publication History

  1. Published Online: 23 AUG 2012
  2. Published Print: 22 AUG 2012

ISBN Information

Print ISBN: 9783527330324

Online ISBN: 9783527646340

SEARCH

Keywords:

  • CMOS;
  • gate dielectrics;
  • gate leakage current;
  • high-k materials;
  • integrated circuit;
  • device scaling

Summary

This chapter contains sections titled:

  • Introduction

  • Scaling and Limitation of CMOS

  • Toward Alternative Gate Stacks Technology

  • Improvements and Alternative to CMOS Technologies

  • Potential Technologies Beyond CMOS

  • Conclusions

  • References