9. Interface Engineering in the High-k Dielectric Gate Stacks

  1. Prof. Gang He and
  2. Prof. Zhaoqi Sun
  1. Shijie Wang1,
  2. Yuanping Feng2 and
  3. Alfred C. H. Huan3

Published Online: 23 AUG 2012

DOI: 10.1002/9783527646340.ch9

High-k Gate Dielectrics for CMOS Technology

High-k Gate Dielectrics for CMOS Technology

How to Cite

Wang, S., Feng, Y. and Huan, A. C. H. (2012) Interface Engineering in the High-k Dielectric Gate Stacks, in High-k Gate Dielectrics for CMOS Technology (eds G. He and Z. Sun), Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim, Germany. doi: 10.1002/9783527646340.ch9

Editor Information

  1. Anhui University, School of Physics and Materials Science, Anhui Key Laboratory of Information Materials and Devices, Feixi Road 3, Hefei 230039, China

Author Information

  1. 1

    A*STAR (Agency for Science, Technology and Research), Institute of Materials Research and Engineering (IMRE), 3 Research Link, Singapore 117602, Singapore

  2. 2

    National University of Singapore, Department of Physics, 2 Science Drive 3, Singapore 117542, Singapore

  3. 3

    Nanyang Technological University, Division of Physics and Applied Physics, School of Physical and Mathematical Sciences, 21 Nanyang Link, Singapore 637371, Singapore

Publication History

  1. Published Online: 23 AUG 2012
  2. Published Print: 22 AUG 2012

ISBN Information

Print ISBN: 9783527330324

Online ISBN: 9783527646340

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Keywords:

  • Keywords: band offset;
  • gate dielectric;
  • heterojunction;
  • high-k dielectric material;
  • metal/semiconductor interfaces;
  • Schottky barrier height

Summary

This chapter contains sections titled:

  • Introduction

  • High-k Oxide/Si Interfaces

  • Metal Gate/High-k Dielectric Interfaces

  • Chemical Tuning of Band Alignments for Metal Gate/High-k Oxide Interfaces

  • Summary and Discussion

  • References