The Effect of Gate-Dielectric Surface Energy on Pentacene Morphology and Organic Field-Effect Transistor Characteristics

Authors


  • This work was supported by the Center for Electronic Packaging Materials of the Korea Science and Engineering Foundation.

Abstract

The effects of the surface energy of polymer gate dielectrics on pentacene morphology and the electrical properties of pentacene field-effect transistors (FETs) are reported, using surface-energy-controllable poly(imide-siloxane)s as gate-dielectric layers. The surface energy of gate dielectrics strongly influences the pentacene film morphology and growth mode, producing Stranski–Krastanov growth with large and dendritic grains at high surface energy and three-dimensional island growth with small grains at low surface energy. In spite of the small grain size (≈ 300 nm) and decreased ordering of pentacene molecules vertical to the gate dielectric with low surface energy, the mobility of FETs with a low-surface-energy gate dielectric is larger by a factor of about five, compared to their high-surface-energy counterparts. In pentacene growth on the low-surface-energy gate dielectric, interconnection between grains is observed and gradual lateral growth of grains causes the vacant space between grains to be filled. Hence, the higher mobility of the FETs with low-surface-energy gate dielectrics can be achieved by interconnection and tight packing between pentacene grains. On the other hand, the high-surface-energy dielectric forms the first pentacene layer with some voids and then successive, incomplete layers over the first, which can limit the transport of charge carriers and cause lower carrier mobility, in spite of the formation of large grains (≈ 1.3 μm) in a thicker pentacene film.

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