Charge Trapping in Intergrain Regions of Pentacene Thin Film Transistors


  • The authors M. T. and M. C. made equal contribution to the work. We gratefully acknowledge funding from the European Science Foundation through the Self-Organised Nanostructures (SONS) initiative (Project 02-PE-SONS-130 NETSOMA), and from Hitachi Europe.


A scanning Kelvin probe microscopy (SKPM) study of the surface potential of vacuum sublimed pentacene transistors under bias stress and its correlation with the film morphology is presented. While for thicker films there are some trapping centers inhomogeneously distributed over the film, as previously reported by other authors, by decreasing the film thickness the effect of thin intergrain regions (IGRs) becomes clear and a very good correlation between the topography and the potential data is observed. It is shown that in the thick pentacene grains the potential is homogeneous and independent of the gate bias applied with negligible charge trapping, while in the thin IGRs the potential varies with the applied gate bias, indicating that only an incomplete accumulation layer can be formed. Clear evidence for preferential charge trapping in the thin IGRs is obtained.