Sources of Hysteresis in Carbon Nanotube Field-Effect Transistors and Their Elimination Via Methylsiloxane Encapsulants and Optimized Growth Procedures

Authors

  • Sung Hun Jin,

    1. Department of Materials Science and Engineering and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA
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  • Ahmad E. Islam,

    1. Department of Materials Science and Engineering and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA
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  • Tae-il Kim,

    1. Department of Materials Science and Engineering and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA
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  • Ji-hun Kim,

    1. Department of Materials Science and Engineering and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA
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  • Muhammad A. Alam,

    1. Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906, USA
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  • John A. Rogers

    Corresponding author
    1. Department of Materials Science and Engineering and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA
    2. Departments of Chemistry, Mechanical Science and Engineering, Electrical, and Computer Engineering, Beckman Institute for Advanced Science and Technology, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA
    • Department of Materials Science and Engineering and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA.
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Abstract

The origins of gate-induced hysteresis in carbon nanotube field-effect transistors are explained and techniques to eliminate this hysteresis with encapsulating layers of methylsiloxane and modified processes for nanotube growth are reported. A combined experimental and theoretical analysis of the dependence of hysteresis on the gate voltage sweep-rate reveals the locations, types, and densities of defects that contribute to hysteresis. Devices with designs that eliminate these defects exhibit more than ten times reduction in hysteresis compared to conventional layouts. Demonstrations in individual transistors that use both networks and arrays of nanotubes, and in simple logic gates built with these devices, illustrate the utility of the proposed approaches.

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