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Decoupling the Bias-Stress-Induced Charge Trapping in Semiconductors and Gate-Dielectrics of Organic Transistors Using a Double Stretched-Exponential Formula

Authors

  • Hyun Ho Choi,

    1. Department of Chemical Engineering, Center for Advanced Soft Electronics (CASE), Pohang University of Science and Technology (POSTECH), Pohang 790-784, Korea
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  • Moon Sung Kang,

    1. Department of Chemical Engineering, Soongsil University, Seoul 156-743, Korea
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  • Min Kim,

    1. Department of Chemical Engineering, Center for Advanced Soft Electronics (CASE), Pohang University of Science and Technology (POSTECH), Pohang 790-784, Korea
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  • Haena Kim,

    1. Department of Chemical Engineering, Center for Advanced Soft Electronics (CASE), Pohang University of Science and Technology (POSTECH), Pohang 790-784, Korea
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  • Jeong Ho Cho,

    Corresponding author
    1. SKKU Advanced Institute of Nanotechnology (SAINT) and Center for Human Interface Nano Technology (HINT), School of Chemical Engineering, Sungkyunkwan University, Suwon 440-476, Korea
    • SKKU Advanced Institute of Nanotechnology (SAINT) and Center for Human Interface Nano Technology (HINT), School of Chemical Engineering, Sungkyunkwan University, Suwon 440-476, Korea.
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  • Kilwon Cho

    Corresponding author
    1. Department of Chemical Engineering, Center for Advanced Soft Electronics (CASE), Pohang University of Science and Technology (POSTECH), Pohang 790-784, Korea
    • Department of Chemical Engineering, Center for Advanced Soft Electronics (CASE), Pohang University of Science and Technology (POSTECH), Pohang 790-784, Korea
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Abstract

A novel strategy for analyzing bias-stress effects in organic field-effect transistors (OFETs) based on a four-parameter double stretched-exponential formula is reported. The formula is obtained by modifying a traditional single stretched-exponential expression comprising two parameters (a characteristic time and a stretched-exponential factor) that describe the bias-stress effects. The expression yields two characteristic times and two stretched-exponential factors, thereby separating out the contributions due to charge trapping events in the semiconductor layer-side of the interface and the gate-dielectric layer-side of the interface. The validity of this method was tested by designing two model systems in which the physical properties of the semiconductor layer and the gate-dielectric layer were varied systematically. It was found that the gate-dielectric layer, in general, plays a more critical role than the semiconductor layer in the bias-stress effects, possibly due to the wider distribution of the activation energy for charge trapping. Furthermore, the presence of a self-assembled monolayer further widens the distribution of the activation energy for charge trapping in gate-dielectric layer-side of the interface and causes the channel current to decay rapidly in the early stages. The novel analysis method presented here enhances our understanding of charge trapping and provides rational guidelines for developing efficient OFETs with high performance.

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