Official contribution of the National Institute of Standards and Technology; not subject to copyright in the United States. The error bars presented throughout this manuscript indicate the relative standard uncertainty of the measurement. Certain commercial materials and equipment are identified in this paper in order to specify adequately the experimental procedure. In no case does such identification imply recommendation by the National Institute of Standards and Technology nor does it imply that the material or equipment identified is necessarily the best available for this purpose. This work was supported in part by the System IC 2010 Project of Korea, the Chemistry and Molecular Engineering Program of Brain Korea 21 Project, and the NIST Office of Microelectronics Programs. We also acknowledge the Nanofabrication Laboratory in the NIST Center for Nanoscale Science and Technology (CNST) for the use of their facilities. Supporting Information is available online from Wiley InterScience or from the authors.
The Direct Patterning of Nanoporous Interlayer Dielectric Insulator Films by Nanoimprint Lithography†
Version of Record online: 29 AUG 2007
Copyright © 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Volume 19, Issue 19, pages 2919–2924, October, 2007
How to Cite
Ro, H. W., Jones, R. L., Peng, H., Hines, D. R., Lee, H.-J., Lin, E. K., Karim, A., Yoon, D. Y., Gidley, D. W. and Soles, C. L. (2007), The Direct Patterning of Nanoporous Interlayer Dielectric Insulator Films by Nanoimprint Lithography. Adv. Mater., 19: 2919–2924. doi: 10.1002/adma.200602872
- Issue online: 1 OCT 2007
- Version of Record online: 29 AUG 2007
- Manuscript Revised: 21 FEB 2007
- Manuscript Received: 14 DEC 2006
- System IC 2010 Project of Korea
- Chemistry and Molecular Engineering Program of Brain Korea 21 Project
- NIST Office of Microelectronics Programs
Supporting information for this article is available on the WWW under http://www.wiley-vch.de/contents/jc_2089/2007/c2872_s.pdf or from the author.
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