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In Figure 4 of the original paper a fifth panel (Figure 4e), which displayed incorrectly calculated parameters, was accidentally included. The correct Figure 4 is displayed here:

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Figure 4. a) Schematic side view of a top-gated SWNT-array transistor that uses a layer of HfO2 as the gate dielectric, Au as the gate electrode, and Pd as source and drain electrodes. b) Optical image of a set of such devices. Oval regions where the HfO2 was removed provide electrical contact points to the source and drain electrodes. c) Id as a function of Vg for Vds = 0.05 V, for a transistor (L = 4 μm; W = 76 μm) that incorporates aligned arrays of SWNTs from single-growth (D ∼4–7 SWNTs μm−1) and from double growth (D ∼7–15 SWNTs μm−1). The open and solid circles indicate the sweep direction of gate voltage (solid – sweep up; open – sweep down). d) Histograms of current measured in the p-channel “on state” (i.e., Vg = −3 V), the “off state” (i.e., Vg is set to realize the minimum Id, typically between 0 and 0.5 V) and the n-channel “on state” (i.e., Vg = 3 V) for transistors built in regions of single growth (black bars) and double growth (red bars).

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