Communication

Enhanced Lithographic Imaging Layer Meets Semiconductor Manufacturing Specification a Decade Early

  1. Yu-Chih Tseng1,
  2. Anil U. Mane2,
  3. Jeffrey W. Elam2,
  4. Seth B. Darling1,*

Article first published online: 10 APR 2012

DOI: 10.1002/adma.201104871

Issue

Advanced Materials

Advanced Materials

Volume 24, Issue 19, pages 2608–2613, May 15, 2012

Additional Information

How to Cite

Tseng, Y.-C., Mane, A. U., Elam, J. W. and Darling, S. B. (2012), Enhanced Lithographic Imaging Layer Meets Semiconductor Manufacturing Specification a Decade Early. Adv. Mater., 24: 2608–2613. doi: 10.1002/adma.201104871

Author Information

  1. 1

    Argonne National Laboratory, Center for Nanoscale Materials, 9700 S. Cass Ave., Argonne, IL, USA

  2. 2

    Argonne National Laboratory, Energy Systems Division, 9700 S. Cass Ave., Argonne, IL, USA

*Argonne National Laboratory, Center for Nanoscale Materials, 9700 S. Cass Ave., Argonne, IL, USA.

Publication History

  1. Issue published online: 9 MAY 2012
  2. Article first published online: 10 APR 2012
  3. Manuscript Received: 21 DEC 2012

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Keywords:

  • lithography;
  • semiconductors;
  • patterning;
  • resists;
  • sequential infiltration synthesis (SIS)
Thumbnail image of graphical abstract

This scanning electron microscopy image (∼2 μm wide) depicts high-aspect-ratio features patterned in silicon using sequential infiltration synthesis (SIS) enhancement of photoresist. SIS penetrates the polymeric resist layer with etch-resistant alumina, thereby transforming it into a hard mask. This conversion enables the use of very thin resist layers, so pattern collapse is virtually eliminated and goals set forth for lithography in 2022 can be achieved today.

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