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Communication

Tailoring of Molecular Planarity to Reduce Charge Injection Barrier for High-Performance Small-Molecule-Based Ternary Memory Device with Low Threshold Voltage

  1. Shifeng Miao1,
  2. Hua Li1,
  3. Qingfeng Xu1,
  4. Youyong Li3,
  5. Shunjun Ji1,
  6. Najun Li1,
  7. Lihua Wang1,
  8. Junwei Zheng2,
  9. Jianmei Lu1,*

Article first published online: 13 SEP 2012

DOI: 10.1002/adma.201202319

Issue

Advanced Materials

Advanced Materials

Volume 24, Issue 46, pages 6210–6215, December 4, 2012

Additional Information

How to Cite

Miao, S., Li, H., Xu, Q., Li, Y., Ji, S., Li, N., Wang, L., Zheng, J. and Lu, J. (2012), Tailoring of Molecular Planarity to Reduce Charge Injection Barrier for High-Performance Small-Molecule-Based Ternary Memory Device with Low Threshold Voltage. Adv. Mater., 24: 6210–6215. doi: 10.1002/adma.201202319

Author Information

  1. 1

    Key Laboratory of Organic Synthesis of Jiangsu Province, College of Chemistry, Chemical Engineering and Materials Science, Soochow University, Suzhou 215123, P. R. China

  2. 2

    Institute of Chemical Power Sources, Soochow University, Suzhou 215006, P. R. China

  3. 3

    Functional Nano & Soft Materials Laboratory (FUNSOM), and Jiangsu Key Laboratory for Carbon-Based Functional, Materials & Devices, Soochow University, Suzhou 215123, P. R. China

*Key Laboratory of Organic Synthesis of Jiangsu Province, College of Chemistry, Chemical Engineering and Materials Science, Soochow University, Suzhou 215123, P. R. China.

Publication History

  1. Issue published online: 29 NOV 2012
  2. Article first published online: 13 SEP 2012
  3. Manuscript Revised: 7 AUG 2012
  4. Manuscript Received: 8 JUN 2012

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Keywords:

  • ternary;
  • memory;
  • small molecule;
  • planarity;
  • threshold voltage
Thumbnail image of graphical abstract

By introducing a coplanar fluorenone into the center of an azo molecule, the turn-on voltages of the ternary memory devices are significantly decreased to lower than –2 V due to the improved crystallinity and the reduced charge injection barrier. The resulting low-power consumption devices will have great potential applications in high-performance chips for future portable nanoelectronic devices.

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