Optimized ASIC/FPGA Design Flow for Energy Efficient Network Nodes
Version of Record online: 27 NOV 2013
Bell Labs Technical Journal
Special Issue: Optical Networking and Technology Innovation
Volume 18, Issue 3, pages 195–209, December 2013
How to Cite
Sahm, H., Sauppe, M., Markert, E., Horn, T., Heinkel, U. and Otto, K.-H. (2013), Optimized ASIC/FPGA Design Flow for Energy Efficient Network Nodes. Bell Labs Tech. J., 18: 195–209. doi: 10.1002/bltj.21634
- Issue online: 27 NOV 2013
- Version of Record online: 27 NOV 2013
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