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Formal system-level design space exploration

Authors

  • Daniel Knorreck,

    Corresponding author
    1. Institut Telecom, Telecom ParisTech, LTCI CNRS 2229, routes des Crêtes, B.P. 193 F-06904 Sophia-Antipolis Cedex, France
    • Correspondence to: Daniel Knorreck, Institut Telecom, Telecom ParisTech, LTCI CNRS 2229, routes des Crêtes, B.P. 193 F-06904 Sophia-Antipolis Cedex, France.

      E-mail: daniel.knorreck@eurecom.fr

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  • Ludovic Apvrille,

    1. Institut Telecom, Telecom ParisTech, LTCI CNRS 2229, routes des Crêtes, B.P. 193 F-06904 Sophia-Antipolis Cedex, France
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  • Renaud Pacalet

    1. Institut Telecom, Telecom ParisTech, LTCI CNRS 2229, routes des Crêtes, B.P. 193 F-06904 Sophia-Antipolis Cedex, France
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SUMMARY

DIPLODOCUS is a UML profile intended for the modeling and the formal verification of real-time and embedded applications commonly executed on complex Systems-on-Chip. DIPLODOCUS implements the Y-chart approach, that is, application and HW architecture (e.g., CPUs, bus, memories) are first described independently and are subsequently related to each other in a mapping stage. Abstract tasks and communication primitives are therefore mapped onto platform elements like buses and CPUs. DIPLODOCUS endows all models with a formal semantics, thereby paving the way for formal proofs both before and after mapping. More concretely, application, architecture, and mapping models can be edited in TTool – an open-source toolkit – using UML diagrams. Then, pre-mapping or post-mapping UML models may be automatically transformed into a LOTOS-based representation. This specification is in turn amenable to model-checking techniques to evaluate properties of the system, for example, safety, schedulability, and performance properties. A smart card system serves as case study to illustrate the formal verification capabilities of DIPLODOCUS. Copyright © 2012 John Wiley & Sons, Ltd.

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