Special Issue Paper
Runtime failure rate targeting for energy-efficient reliability in chip microprocessors
Version of Record online: 10 JUL 2012
Copyright © 2012 John Wiley & Sons, Ltd.
Concurrency and Computation: Practice and Experience
Special Issue: Latest Trends in Computer Architectures and Parallel and Distributed Technologies
Volume 25, Issue 6, pages 790–807, 25 April 2013
How to Cite
Miller, T., Surapaneni, N. and Teodorescu, R. (2013), Runtime failure rate targeting for energy-efficient reliability in chip microprocessors. Concurrency Computat.: Pract. Exper., 25: 790–807. doi: 10.1002/cpe.2898
- Issue online: 18 MAR 2013
- Version of Record online: 10 JUL 2012
- Manuscript Accepted: 10 MAY 2012
- Manuscript Revised: 22 APR 2012
- Manuscript Received: 19 MAY 2011
- National Science Foundation. Grant Number: CNS-0403342
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