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Reducing thread divergence in a GPU-accelerated branch-and-bound algorithm


Correspondence to: I. Chakroun, Université Lille 1 CNRS/LIFL, INRIA Lille Nord Europe, Cité scientifique - 59655, Villeneuve d'Ascq cedex, France.



In this paper, we address the design and implementation of graphical processing unit (GPU)-accelerated branch-and-bound algorithms (B&B) for solving flow-shop scheduling optimization problems (FSP). Such applications are CPU-time consuming and highly irregular. On the other hand, GPUs are massively multithreaded accelerators using the single instruction multiple data model at execution. A major issue that arises when executing on GPU, a B&B applied to FSP is thread or branch divergence. Such divergence is caused by the lower bound function of FSP that contains many irregular loops and conditional instructions. Our challenge is therefore to revisit the design and implementation of B&B applied to FSP dealing with thread divergence. Extensive experiments of the proposed approach have been carried out on well-known FSP benchmarks using an Nvidia Tesla (C2050 GPU card ( Compared with a CPU-based execution, accelerations up to × 77.46 are achieved for large problem instances. Copyright © 2012 John Wiley & Sons, Ltd.

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