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Keywords:

  • cache coherence;
  • real-time;
  • processor architecture

SUMMARY

In multicore systems, the concurrent access to shared data generates a bottleneck for the system performance. Cache coherence techniques have been introduced to enable fast access while preserving the data coherence, but these coherence protocols are critical in hard real-time systems. Because the frequent inter-cache communication leads to unpredictable interferences between the cores, the system's timing behaviour is hard to analyse. In this paper, we propose a new, hard real-time capable strategy for multicore systems called on-demand coherent cache (ODC2). The technique is based on marginal hardware extensions compared with noncoherent caches and the use of common synchronisation techniques. ODC2 provides coherent accesses to cached shared data as well as caching of private data. Because the presented strategy does not induce interferences between local caches, ODC2 is capable for hard real-time systems. We present an evaluation of performance and scalability of ODC2 compared with two standard coherence protocols using a bus-based multicore system. Copyright © 2013 John Wiley & Sons, Ltd.