Research Article

A parallel Viterbi decoding algorithm

  1. J. S. Reeve*

Article first published online: 27 FEB 2001

DOI: 10.1002/cpe.539

Issue

Concurrency and Computation: Practice and Experience

Concurrency and Computation: Practice and Experience

Volume 13, Issue 2, pages 95–102, February 2001

Additional Information

How to Cite

Reeve, J. S. (2001), A parallel Viterbi decoding algorithm. Concurrency and Computation: Practice and Experience, 13: 95–102. doi: 10.1002/cpe.539

Author Information

  1. Department of Electronics and Computer Science, University of Southampton, Southampton SO17 1BJ, U.K.

*Department of Electronics and Computer Science, University of Southampton, Southampton SO17 1BJ, U.K.

Publication History

  1. Issue published online: 27 FEB 2001
  2. Article first published online: 27 FEB 2001
  3. Manuscript Revised: 27 JUL 2000
  4. Manuscript Received: 24 NOV 1999

SEARCH

SEARCH BY CITATION

ARTICLE TOOLS

Get PDF (237K)

Keywords:

  • trellis decoding;
  • Viterbi decoding;
  • BCH codes

Abstract

In this paper we express the Viterbi algorithm as a matrix–vector reduction in which multiplication is replaced by addition and addition by minimization. The resulting algorithm is then readily parallelized in a form suitable for implementation on a systolic processor array. We describe the algorithm for Bose–Chaudhuri–Hocquenghem (BCH) codes which have a task graph with its valence restricted to four inputs and four outputs. The method is also applicable to convolution codes, but the complexity of the task graph increases with the number of input bits for these codes. Results for BCH codes are given for two general purpose parallel machines, an IBM SP2 and a Meiko CS2. Copyright © 2001 John Wiley & Sons, Ltd.

Get PDF (237K)