In this work, the benefits of memristor-based multilevel memories are described along with their design problems. Starting with measurements of discrete actual devices, a discrete memristor-based multilevel memory is developed. It uses a printed circuit board in order to connect eight packaged memristors from Bio Inspired to test a ternary arithmetic logic unit on a field programmable gate array. These circuits are then integrated in the second proposed memory system based on a 150-nm CMOS process that can be equipped with memristors on top of the metal layers. This integrated solution includes proper read-out, erase, and write circuits to control real memristors and 32×32 memristive memory cells. It is compared with a common static random-access memory in terms of area, computation speed, and power consumption showing benefits for memory sizes bigger than 70 words. Because yield and device variations are still a big issue in memristor fabrication, methods to counter these problems are also proposed in the end. An actual implementation should offer several trimming solutions to ensure proper functionality of a prototype memory as well as a power-on calibration, until these problems are solved. The development of the presented memories is not only based on different models but also based on measurements done with real devices. Copyright © 2017 John Wiley & Sons, Ltd.